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at28c010 com/ind 1 megabit (128k x 8) paged cmos e 2 prom commercial and industrial features fast read access time - 120 ns automatic page write operation internal address and data latches for 128-bytes internal control timer fast write cycle time page write cycle time - 10 ms maximum 1 to 128-byte page write operation low power dissipation 40 ma active current 200 m a cmos standby current hardware and software data protection data polling for end of write detection high reliability cmos technology endurance: 10 4 or 10 5 cycles data retention: 10 years single 5v 10% supply cmos and ttl compatible inputs and outputs jedec approved byte-wide pinout commercial and industrial temperature ranges description the at28c010 is a high-performance electrically erasable and programmable read only memory. its 1 megabit of memory is organized as 131,072 words by 8 bits. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 120 ns with power dissipation of just 220 mw. when the device is deselected, the cmos standby current is less than 200 m a. (continued) pdip top view pin name function a0 - a16 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc dont connect pin configurations tsop top view plcc top view note: plcc package pin 1 is a dont connect. 0353c at28c010 com/ind 2-231
block diagram temperature under bias................. -55c to +125c storage temperature...................... -65c to +150c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* the at28c010 is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 128-byte page register to allow writ- ing of up to 128-bytes simultaneously. during a write cy- cle, the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other opera- tions. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. atmels 28c010 has additional features to ensure high quality and manufacturability. the device utilizes internal error correction for extended endurance and improved data retention characteristics. an optional software data protection mechanism is available to guard against inad- vertent writes. the device also includes an extra 128- bytes of e 2 prom for device identification or tracking. description (continued) 2-232 at28c010 com/ind
device operation read: the at28c010 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual- line control gives designers flexibility in preventing bus contention in their system. byte write: a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cy- cle. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. once a byte write has been started it will automatically time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effectively be a poll- ing operation. page write: the page write operation of the at28c010 allows 1 to 128-bytes of data to be written into the device during a single internal programming period. a page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 ad- ditional bytes. each successive byte must be written within 150 m s (t blc ) of the previous byte. if the t blc limit is ex- ceeded the at28c010 will cease accepting data and com- mence the internal programming operation. all bytes dur- ing a page write operation must reside on the same page as defined by the state of the a7 - a16 inputs. for each we high to low transition during the page write operation, a7 - a16 must be the same. the a0 to a6 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. data polling: the at28c010 features data polling to indicate the end of a write cycle. during a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be pre- sented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle. toggle bit: in addition to data polling the at28c010 provides another method for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling be- tween one and zero. once the write has completed, i/o6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. data protection: if precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. hardware protection: hardware features protect against inadvertent writes to the at28c010 in the follow- ing ways: (a) v cc sense - if v cc is below 3.8v (typical) the write function is inhibited; (b) v cc power-on delay - once v cc has reached 3.8v the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of oe low, ce high or we high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typi- cal) on the we or ce inputs will not initiate a write cycle. software data protection: a software controlled data protection feature has been implemented on the at28c010. when enabled, the software data protection (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user; the at28c010 is shipped from atmel with sdp disabled. sdp is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to software data protection algorithm). after writing the 3-byte command sequence and after t wc the entire at28c010 will be pro- tected against inadvertent write operations. it should be noted, that once protected the host may still perform a byte or page write to the at28c010. this is done by pre- ceding the data to be written by the same 3-byte command sequence used to enable sdp. once set, sdp will remain active unless the disable com- mand sequence is issued. power transitions do not dis- able sdp and sdp will protect the at28c010 during power-up and power-down conditions. all command se- quences must conform to the page write timing specifica- tions. the data in the enable and disable command se- quences is not written to the device and the memory ad- dresses used in the sequence may be written with data in either a byte or page write operation. after setting sdp, any attempt to write to the device with- out the 3-byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , read operations will effectively be polling operations. (continued) at28c010 com/ind 2-233
mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. operating modes symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc + 1v 200 m a i sb2 v cc standby current ttl ce = 2.0v to v cc + 1v 3 ma i cc v cc active current f = 5 mhz; i out = 0 ma 40 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma .45 v v oh1 output high voltage i oh = -400 m a 2.4 v v oh2 output high voltage cmos i oh = -100 m a; v cc = 4.5v 4.2 v dc characteristics at28c010-12 at28c010-15 at28c010-20 operating temperature (case) com. 0c - 70c 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c -40c - 85c v cc power supply 5v 10% 5v 10% 5v 10% dc and ac operating range device identification: an extra 128-bytes of e 2 prom memory are available to the user for device identification. by raising a9 to 12v 0.5v and using ad- dress locations 1ff80h to 1ffffh the bytes may be writ- ten to or read from in the same manner as the regular memory array. optional chip erase mode: the entire device can be erased using a 6-byte software code. please see soft- ware chip erase application note for details. device operation (continued) 2-234 at28c010 com/ind
at28c010-12 at28c010-15 at28c010-20 symbol parameter min max min max min max units t acc address to output delay 120 150 200 ns t ce (1) ce to output delay 120 150 200 ns t oe (2) oe to output delay 0 50 0 55 0 55 ns t df (3, 4) ce or oe to output float 0 50 0 55 0 55 ns t oh output hold from oe, ce or address, whichever occurred first 000ns ac read characteristics notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read waveforms (1, 2, 3, 4) t r , t f < 5 ns input test waveforms and measurement level output test load typ max units conditions c in 410pfv in = 0v c out 812pfv out = 0v pin capacitance (f = 1 mhz, t = 25c) (1) note: 1. this parameter is characterized and is not 100% tested. at28c010 com/ind 2-235
symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 100 ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns ac write characteristics ac write waveforms we controlled ce controlled 2-236 at28c010 com/ind
symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 100 ns t blc byte load cycle time 150 m s t wph write pulse width high 50 ns page mode characteristics page mode write waveforms (1, 2) notes: 1. a7 through a16 must specify the page address during each high to low transition of we (or ce). 2. oe must be high only when we and ce are both low. chip erase waveforms t s = 5 m sec (min.) t w = t h = 10 msec (min.) v h = 12.0v 0.5v at28c010 com/ind 2-237
load last byte to last address load data a0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128-bytes of data are loaded. enter data protect state writes enabled (2) software data protection enable algorithm (1) load data xx to any address (4) load last byte to last address load data 55 to address 2aaa load data aa to address 5555 load data 80 to address 5555 load data 55 to address 2aaa load data aa to address 5555 load data 20 to address 5555 exit data protect state (3) software data protection disable algorithm (1) load data xx to any address (4) software protected program cycle waveform (1, 2, 3) notes: 1. a0 - a14 must conform to the addressing sequence for the first 3-bytes as shown above. 2. after the command sequence has been issued and a page write operation follows, the page address inputs (a7 - a16) must be the same for each high to low transition of we (or ce). 3. oe must be high only when we and ce are both low. 2-238 at28c010 com/ind
symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns data polling characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. data polling waveforms symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns notes: 1. these parameters are characterized and not 100% tested. toggle bit characteristics (1) 2. see ac read characteristics. notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. toggle bit waveforms 3. any address location may be used but the address should not vary. at28c010 com/ind 2-239
t acc (ns) i cc (ma) ordering code package operation range active standby 120 40 0.2 at28c010(e)-12jc 32j commercial at28c010(e)-12pc 32p6 (0 to 70 c) at28c010(e)-12tc 32t 40 0.2 at28c010(e)-12ji 32j industrial at28c010(e)-12pi 32p6 (-40 to 85 c) at28c010(e)-12ti 32t 150 40 0.2 at28c010(e)-15jc 32j commercial at28c010(e)-15pc 32p6 (0 to 70 c) at28c010(e)-15tc 32t 40 0.2 at28c010(e)-15ji 32j industrial at28c010(e)-15pi 32p6 (-40 to 85 c) at28c010(e)-15ti 32t 200 40 0.2 at28c010(e)-20jc 32j commercial at28c010(e)-20pc 32p6 (0 to 70 c) at28c010(e)-20tc 32t 40 0.2 at28c010(e)-20ji 32j industrial at28c010(e)-20pi 32p6 (-40 to 85 c) at28c010(e)-20ti 32t 40 0.2 at28c010-w die commercial (0 to 70 c) ordering information (1) note: 1. see valid part number table below. the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28c010 12 jc, ji, pc, pi, tc, ti at28c010e 12 jc, ji, pc, pi, tc, ti at28c010 15 jc, ji, pc, pi, tc, ti at28c010e 15 jc, ji, pc, pi, tc, ti at28c010 20 jc, ji, pc, pi, tc, ti at28c010e 20 jc, ji, pc, pi, tc, ti at28c010 - w valid part numbers 2-240 at28c010 com/ind
package type 32j 32 lead, plastic j-leaded chip carrier (plcc) 32p6 32 lead, 0.600" wide, plastic dual inline package (pdip) 32t 32 lead, plastic thin small outline package (tsop) w die options blank standard device: endurance = 10k write cycles; write time = 10 ms e high endurance option: endurance = 100k write cycles at28c010 com/ind 2-241

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